The 2025 Semiconductor CMOS Practical Program will be held for six days from Monday, July 28th to Saturday, August 2nd, 2025.

We are recruiting participants for this program as follows.

Practical training theme: CMOS transistor and IC fabrication training

Date: 6 days from Monday, July 28th to Saturday, August 2nd, 2025

Number of participants: 7 people (participation fee: 60,000 yen)

How to attend: On-site training and lectures.

Venue: Hiroshima University Semiconductor Industrial Technology Research Institute RISE

(Super clean room (highest class 10, floor area 830m2) used)

Training content: Learn basic process technology and the overall basic technology of transistors and circuits through practical training in prototyping CMOS integrated circuits using NMOS and PMOS transistors. Learn basic technologies such as ion implantation, oxidation, lithography, and etching. The circuits to be fabricated include ring oscillators and SRAMs based on CMOS inverters. To save time, preparations will be made in advance up to the formation of the N-well. Students will design transistor circuits and fabricate devices together with the Institute's staff, and after fabricating the devices, they will evaluate the characteristics of the devices and circuits they have designed. Through this, students will learn about the entire fabrication process and the knowledge it requires. Lectures will also be given to further deepen their understanding.

How to apply:

- Please apply via the web page below.

The application deadline is 5:00 p.m. on Monday, June 23rd.

When applying, please also include a reason for applying.

https://forms.cloud.microsoft/r/XYFMEbdgeh

Selection method:

- Applicants will be screened and selected based on their reasons for applying.

Notification of acceptance: Monday, June 30th, 2025